Great work so far. Looks like you've had to go farther than anyone else!Tigertron wrote:...A schematic of this circuit would really save my eyes. Has anyone got one?...
Yes, you will have to use higher power optical magnification! R39 is marked "43D", and R40 "41C". They are special value, or at least, 1% tolerance devices.Tigertron wrote:I found two chip resistors R39 and R40 that seem to be marked 430 and 410.
Yes, the 339 is a quad op-amp designed for comparator service. iRbt uses them all over the place. When an ordinary op-amp is required, its the LM324 that you'll see.... The junction of the two resistors heads off to a input (pin 7) of the LM339 (quad opamp). I see feedback resistors and it looks like its a comparator ..
I'll work on those measurements later.... you could measure a voltage {on} T28. Also pin 6 and pin 1 voltages of the LM339 would be helpful. ...
I have pencil drafts of the HB's circuit sections, but have no plans to make digital images of each section. I think the work involved is not warranted. During the last few days that I was able to work on the HB-project I formulated the idea of preparing a quasi block/schematic diagram of the entire HB, which I would then post in this thread. The pencil-sketch of that diagram requires more work, but if you need a copy I could try scanning it, then attaching it to a PM for you. I expect some weeks will pass before I will be allocated time to make a clean CAD image of the diagram.klapskalli wrote:...did you get to create a schematic of the home base?
Looks like they have been mixed! Here are my notes for those two:I've bought a used DISCO and it's home base isn't working ... i was able to find out that the regulator (K78L05A) right to the point "T_VCC" was broke and replaced it. ...We replaced the capacitors (4.7muF & 100muF) ... too.
I'm not sure, if ... we mixed them up (left <-> right). Now, the 100uF capacitor is closest to the edge of the board, the 4.7uF capacitor closer to the middle of the board. Is that right?
Tim, I expect those three features will all work as soon as you discover/correct the remaining fault(s).There definitely are 5.02v on the "T_VCC" point. But the home base still doesn't work right:
- Power LED lights up, now
- docking LED is always on, even when not docked
- there is no 4.7v voltage on the charging contacts
- and no 22v when docked. ...
T1;U3-8; (same as 'JUMP_1")
T1(25,35) V_T1 = 0 to 5Vpk, 38kHz SQ-wave (noisy & w/over-shoot).
IoDS (Independent of Docked State).
T2;Q2c;
T2(27,45) V_T2 = 0 to 22Vpk, 38kHz SQ-wave, (wrinkled crest) IoDS.
T3;U3-16;==>R4:R4==>Q1b
T3(23,33) V_T3 = 0 to 5Vpk ~SQ-wave (75% HI,25% LO), with 4.5 to
5Vpk, 38kHz ~SQ-wave, 65% HI, 35% LO. If state=doc'd, V_T3 = 0V.
See T1vsT3signals.jpg, or .apc. T3 shows raw Lft-bcn's signal.
Compare to radiant waveform.
T4;Q1e;
T4(13,31) V_T4 = 0 to 4.2Vpk ~SQ-wave (75% HI,25% LO, with 0.3V to
4.2Vpk, 38kHz ~SQ-wave 65% HI, 35% LO. If state=doc'd, V_T4 = 0V.
See T4_Ndocd.jpg, or .apc, & T4_Ndkd_pulsePkt.jpg. T4 provides a
measure of Lft-bcn's drive-current:
<I_lft_bcn> ~ (.75)*(.5)*(Vpk_T4 - Vmin_T4) / 100.
Lft-bcn's IRED-current sensing (100 ohm emitter res.).
Compare T4_WF to radiant waveform.
T5;U3-15;==>R18:R18==>Q7b
T5(62,40) V_T5 = 0 to 5Vpk PWM wave, with 4.5 to 5Vpk, 38kHz ~SQ-
wave. 8-bit words occupy NOM 40ms frames. A 'one-bit' is described
by 3ms @ 5V + 1ms @ 0V, and a zero-bit by: 1ms @ 0V + 3ms @ 5V.
The RIGHT-beacon's source (U3-15) signal is 11110100 = $F4 = 244
decimal. If state = doc'd, V_T5 = 0V. See T5_Ndocd.jpg, or .apc.
Compare to radiant waveform.
T6;Q7e;
T6(58,44) V_T6 = 0 to 5Vpk PCM wave, with 0.5 to 5Vpk, 38kHz ~SQ-
wave. As with T5 the RIGHT-beacon's PWM code is 11110100 = $F4 =
244 decimal. If state = doc'd, V_T5 = 0V. See T6_Ndocd.jpg,
or .apc. Compare to radiant waveform. Right-bcn's IRED-current
sensing (100 ohm emitter res.).
T7;U3-14; ==>R14:R14==>Q5b
T7(52,39) V_T7 = 0 to 5Vpk PWM wave, with 4.5 to 5Vpk, 38kHz ~SQ-
wave. 8-bit words occupy NOM 40ms frames. A 'one-bit' is described
by 3ms @ 5V + 1ms @ 0V, and a zero-bit by: 1ms @ 0V + 3ms @ 5V.
The Frc-Fld-beacon's source (U3-14) signal is 11110010 = $F2 = 242
decimal. If state = doc'd, V_T7 = 0V. See T7_Ndocd.jpg, or .apc.
Compare to radiant waveform.
T8;Q5e;
T8(39,39) V_T8 = 0 to 4Vpk PCM wave (clean). As with T7 the Frc-
Fld-beacon's source (U3-14) signal is 11110010 = $F2 = 242
decimal. If state = doc'd, V_T5 = 0V. See T8_Ndocd.jpg, or .apc.
Compare to radiant waveform. Frc-Fld-bcn's IRED-current sensing
(47 ohm emitter res.).
T9;U3-13; ==>C14[1,2]
T9(68,41) V_T9 = 0Vdc Ndoc'd, 4.5Vdc doc'd, for Docked-LED drvr.
T10;Q9c; Docked-LED driver
T10(71,46) V_T10 = 3.5Vdc Ndoc'd, ~0Vdc doc'd & Docked-LED ON.
T11;F1(OUT);
T11(15,14) V_T11 = 22.0Vdc, NOM, input from Fast Charger SMPS.
T12;U1(IN+);
T12(19,26) V_T12 = V_78L05(IN+) = 20.8Vdc (w/~0.3V ripple).
T13;U3-5;
T13(63,13) V_T13 = 0 to 5Vpk, 32Hz SQ-wave, IoDS.
T14;D5K;
T14(59,19) 0.86 < V_T14 < 3.2V odd wave, at 32Hz. An IoDS periodic
pulse-train is seen at T14. Its best to view the scope trace (see
T14_Ndoc.jpg) because precisely describing the wave needs many
words. One may try by visualizing pulses formed by slightly
differentiating a 32hZ square-wave. Its rise is no longer instant,
but takes about 7% of the overall pulse-width to reach the 3.2V
peak. Rolling over the peak, there is a -0.6V droop (spanning
~half the pulse-width), after which voltage drops in the manner of
an R*C discharge curve to zero, completing one pulse in the wave-
train.
T15;Q4e & Q6c;
T15(43,28) V_T15 = 0.015Vdc {~0V} Ndoc'd. When state=doc'd, the
signal changes to an ~saw-tooth waveform (SEE T15_docd.jpg)
exhibiting ~0.08VPP, 32Hz.
T16;U3-4;
T16(62,15) V_T16 = 0V, Ndoc'd, but when doc'd V_T16 goes HI to 5V,
and narrow timing notches fall to zero at 5Hz rate. See
T16_docd.jpg. Timing-notches are 2ms wide.
T17;Q4c;
T17(37,23) V_T17 = 21.6Vdc, Ndoc'd, but when state = doc'd V_T17
goes LO to zero, and with narrow timing pips rising to 5Vpk at 5Hz
rate. Timing-pips are ~2ms wide.
T18;U3-3;
T18(60,11) V_T18 = 0 to 5VPP, 32Hz SQ-wave, IoDS.
T19;U4A2-6{IN-};
T19(74,38) V_T19 = 0.3VPP, 32Hz sawtooth, IoDS. See T19_Ndocd.jpg.
T20;U4A2-7{IN+};
T20(89,24) V_T20 = 2.73Vdc, IoDS. This is a fixed reference
voltage for the comparator's non-inverting input.
T21;U4A2-1{OUT};
T21(85,35) V_T21 = 4.96V, IoDS. U4A2's function remains unknown.
T22;Q8b;
T22(65,37) V_T22 = 0.01V, IoDS. Q8's function remains unknown.
T23;D9K;
T23(62,33) V_T23 = 0.01V, IoDS. This function remains unknown. An
input should reside on this node, but there is none!
T24;U4A4-11{IN+};
T24(97,29) V_T24 = 2.93Vdc, IoDS. This is a fixed reference
voltage for the comparator's non-inverting input.
T25;U4A3-8{IN-};
T25(96,24) V_T25 = 2.00Vdc, IoDS. This is a fixed reference
voltage for the comparator's inverting input.
T26;U3-12;
T26(100,15) V_T26 = 0Vdc while state = Ndoc'd, however, during
docking a single, ~19ms wide, 4.8V pulse occurs.
T27;U4A1-5{IN+};
T27(88,30) V_T27 = 2.52Vdc, IoDS. This is a fixed reference
voltage for the comparator's non-inverting input.
T28;
T28;U4A1-4{IN-}; AND T30
ChA = T28(95,4) = U4-4 = U4A1-4{IN-},
ChB = T30(65,5) = D7K, at moment of simulated docking.
Docking was induced by switching 4.7k ohms across HB-output
terminals at "J2".
T28(cont.)
V_T28 is the fractional sample (~8.5%) of V_T30 that is input to
the inverting input (pin-4) of comparator U4A1, (section-1). That
input signal is compared to ~1/2 of +5VREG, which biases non-
inverting input pin-5 of U4.
T28(cont.)
Scope measurements reveal the following actions as a docking event
takes place. Note that these data derive from a simulated docking
in which no charging current flows, only a charging-level voltage
is switched ON.
T28(cont.)
TP Sig- Pre-doc'g Doc'g Post-doc'g Comments / Notes
Name (volts) (volts) (volts)
V_T28 0.37 0.2 1.85 dt_Dock'g ~ 30ms wide,[(1)]
V_T30 4.37 2.0 21.5 dt_Dock'g ~ 30ms wide,[(1)]
T28(cont.)
----------------
T28 & T30 NOTES:
[(1)] Both Post-doc'g signals are seen to be merged with periodic
switch-off pulses of ~1ms width and occurring every 200ms. These
pulses are injected via U2's gate-driver.
----------------
T29;U3-11;
T29(98,10) V_T29 = 5Vdc, IoDS, but it should go LO when U4A1-OUT
goes LO. The function of U4A1 remains unknown.
T30;D7K;
T30(65,5) See above T28 & T30 combined data.
T_GND;
T_GND(10,2) 0.00V NOM reference point, only.
T_VCC;
T_VCC(14,22) +5.00V NOM reference point, only.
The following non-TP device-pins' data may also be of interest.
U3(74,14);
U3-1 V_U3_1 = 0Vdc, IoDS.
U3(74,14);
U3-2 V_U3_2 = 4.96Vdc, IoDS.
U3(74,14);
U3-6 V_U3_6 = 0Vdc, IoDS. This is COB GND.
U3(74,14);
U3-7 V_U3_7 = 5Vdc, IoDS. This may be COB VCC.
U3(74,14);
U3-9 V_U3_9 = 5Vdc, IoDS. This is a soft +5V bias into U3.
U3(74,14);
U3-10 V_U3_10 = 5Vdc, IoDS. This is a soft +5V bias into U3.
U4(93,30);
U4A1-2 V_U4_2 = 5Vdc, Iods.
U4(93,30);
U4-3 This is U4's VCC = +5Vdc.
U4(93,30);
U4A3-9 V_U4_9 = 4.78Vdc when state = Ndocd. If state = docd, then
~1ms wide timing notches fall from the 5V level to 2.7 volts every
200ms.
U4(93,30);
U4A4-10 V_U4_10 = V_U4_9 since pins are on the same node.
U4(93,30);
U4-12 This is U4's GND.
U4(93,30);
U4A4-13 V_U4_13 = 0Vdc when state = Ndocd. If state = docd, then
~1ms wide timing notches rise from the zero level up to 4.8V every
200ms.
U4(93,30);
U4A3-14 V_U4_14 = V_U4_13 since pins are on the same node.
U2(32,28);
U2[1,1]G V_U2G = 21.6V when state = Ndoc'd. If state = doc'd,
then V_U2G pulls down to 2V for 199ms then rises to 21.6V for
1ms, and repeating that sequence every 200ms. The FET conducts
while the gate voltage is LO.
I trust you are messing with this HB for the fun of it, rather than being pressed to get it working!

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